K-micro offers burst-mode CDR for XG-PON1 OLTs

Kawasaki Microelectronics America, Inc. (K-micro) has unveiled a burst-mode CDR SerDes PHY for XG-PON1 OLT applications. Available now in 65-nm and 40-nm process technologies for ASIC integration, the chip is designed to lock to upstream data bursts at 2.488 Gbps in less than 16 bits. K-micro says the CDR SerDes also can be configured to improve burst-mode lock time in GPON OLTs at 1.25 Gbps.

The SerDes is also available as a standalone chip for supporting reference designs.

The SerDes is designed to be tailored according to optical transceiver characteristics and other system characteristics and latencies. The CDR has a jitter tolerance of 0.6 UI in burst mode operation. Outside the burst-mode operation, the CDR works in continuous mode where it can tolerate even higher jitter, K-micro asserts.

Other features K-micro indentified include:

Smart BIST – the ability to test in production a variety of test patterns that emulate a real system environment

High jitter tolerance

Low jitter generation

Easily configuration for all ONU and OLT applications in 10G XG-PON1, GPON, and EPON.

Evaluation chips are available now to qualified ASIC customers at no charge.

September 17, 2011

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